Lines Matching defs:mlx5_hca_attr
152 struct mlx5_hca_attr { struct
153 uint32_t eswitch_manager:1;
154 uint32_t flow_counters_dump:1;
155 uint32_t mem_rq_rmp:1;
156 uint32_t log_max_rmp:5;
157 uint32_t log_max_rqt_size:5;
158 uint32_t parse_graph_flex_node:1;
159 uint8_t flow_counter_bulk_alloc_bitmap;
160 uint32_t eth_net_offloads:1;
161 uint32_t eth_virt:1;
162 uint32_t wqe_vlan_insert:1;
163 uint32_t csum_cap:1;
164 uint32_t vlan_cap:1;
165 uint32_t wqe_inline_mode:2;
166 uint32_t vport_inline_mode:3;
167 uint32_t tunnel_stateless_geneve_rx:1;
168 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
169 uint32_t tunnel_stateless_gtp:1;
170 uint32_t max_lso_cap;
171 uint32_t scatter_fcs:1;
172 uint32_t lro_cap:1;
173 uint32_t tunnel_lro_gre:1;
174 uint32_t tunnel_lro_vxlan:1;
175 uint32_t tunnel_stateless_gre:1;
176 uint32_t tunnel_stateless_vxlan:1;
177 uint32_t swp:1;
178 uint32_t swp_csum:1;
179 uint32_t swp_lso:1;
180 uint32_t lro_max_msg_sz_mode:2;
181 uint32_t rq_delay_drop:1;
182 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
183 uint16_t lro_min_mss_size;
184 uint32_t flex_parser_protocols;
185 uint32_t max_geneve_tlv_options;
186 uint32_t max_geneve_tlv_option_data_len;
187 uint32_t hairpin:1;
188 uint32_t log_max_hairpin_queues:5;
189 uint32_t log_max_hairpin_wq_data_sz:5;
190 uint32_t log_max_hairpin_num_packets:5;
191 uint32_t vhca_id:16;
192 uint32_t relaxed_ordering_write:1;
193 uint32_t relaxed_ordering_read:1;
194 uint32_t access_register_user:1;
195 uint32_t wqe_index_ignore:1;
196 uint32_t cross_channel:1;
197 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
198 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
199 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */
200 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
201 uint32_t scatter_fcs_w_decap_disable:1;
202 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */
203 uint32_t roce:1;
204 uint32_t wait_on_time:1;
205 uint32_t rq_ts_format:2;
206 uint32_t sq_ts_format:2;
207 uint32_t steering_format_version:4;
208 uint32_t qp_ts_format:2;
209 uint32_t regexp_params:1;
210 uint32_t regexp_version:3;
211 uint32_t reg_c_preserve:1;
212 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */
213 uint32_t crypto:1; /* Crypto engine is supported. */
214 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */
215 uint32_t dek:1; /* General obj type DEK is supported. */
216 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */
217 uint32_t credential:1; /* General obj type CREDENTIAL supported. */
218 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */
219 uint32_t regexp_num_of_engines;
220 uint32_t log_max_ft_sampler_num:8;
221 uint32_t inner_ipv4_ihl:1;
222 uint32_t outer_ipv4_ihl:1;
223 uint32_t geneve_tlv_opt;
224 uint32_t cqe_compression:1;
225 uint32_t mini_cqe_resp_flow_tag:1;
226 uint32_t mini_cqe_resp_l3_l4_tag:1;
227 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */
228 struct mlx5_hca_qos_attr qos;
229 struct mlx5_hca_vdpa_attr vdpa;
230 struct mlx5_hca_flow_attr flow;
231 struct mlx5_hca_flex_attr flex;
232 int log_max_qp_sz;
233 int log_max_cq_sz;
234 int log_max_qp;
235 int log_max_cq;
236 uint32_t log_max_pd;
237 uint32_t log_max_mrw_sz;
238 uint32_t log_max_srq;
239 uint32_t log_max_srq_sz;
240 uint32_t rss_ind_tbl_cap;
241 uint32_t mmo_dma_sq_en:1;
242 uint32_t mmo_compress_sq_en:1;
243 uint32_t mmo_decompress_sq_en:1;
244 uint32_t mmo_dma_qp_en:1;
245 uint32_t mmo_compress_qp_en:1;
246 uint32_t mmo_decompress_qp_en:1;
247 uint32_t mmo_regex_qp_en:1;
248 uint32_t mmo_regex_sq_en:1;
249 uint32_t compress_min_block_size:4;
250 uint32_t log_max_mmo_dma:5;
251 uint32_t log_max_mmo_compress:5;
252 uint32_t log_max_mmo_decompress:5;
253 uint32_t umr_modify_entity_size_disabled:1;
254 uint32_t umr_indirect_mkey_disabled:1;
255 uint32_t log_min_stride_wqe_sz:5;
256 uint32_t esw_mgr_vport_id_valid:1; /* E-Switch Mgr vport ID is valid. */
257 uint16_t esw_mgr_vport_id; /* E-Switch Mgr vport ID . */
258 uint16_t max_wqe_sz_sq;