282 #define COMP_BURST_SZ	16  macro
290 	enum rte_dma_status_code status[COMP_BURST_SZ];  in test_failure_in_full_burst()
300 	for (i = 0; i < COMP_BURST_SZ; i++) {  in test_failure_in_full_burst()
312 	if (stats.submitted != baseline.submitted + COMP_BURST_SZ)  in test_failure_in_full_burst()
314 				stats.submitted, baseline.submitted + COMP_BURST_SZ);  in test_failure_in_full_burst()
318 	count = rte_dma_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error);  in test_failure_in_full_burst()
331 		if (rte_dma_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error) != 0  in test_failure_in_full_burst()
336 	status_count = rte_dma_completed_status(dev_id, vchan, COMP_BURST_SZ,  in test_failure_in_full_burst()
344 		status_count += rte_dma_completed_status(dev_id, vchan, COMP_BURST_SZ - 1,  in test_failure_in_full_burst()
348 	if (status_count != COMP_BURST_SZ - count)  in test_failure_in_full_burst()
350 				fail_idx, status_count, COMP_BURST_SZ - count);  in test_failure_in_full_burst()
362 					fail_idx, count + i, COMP_BURST_SZ);  in test_failure_in_full_burst()
366 	if (stats.completed != baseline.completed + COMP_BURST_SZ)  in test_failure_in_full_burst()
368 				stats.completed, baseline.completed + COMP_BURST_SZ);  in test_failure_in_full_burst()
383 	enum rte_dma_status_code status[COMP_BURST_SZ];  in test_individual_status_query_with_failure()
390 	for (j = 0; j < COMP_BURST_SZ; j++) {  in test_individual_status_query_with_failure()
407 		if (n > 1 || count >= COMP_BURST_SZ)  in test_individual_status_query_with_failure()
418 	while (count + status_count < COMP_BURST_SZ) {  in test_individual_status_query_with_failure()
453 	for (j = 0; j < COMP_BURST_SZ; j++) {  in test_single_item_status_query_with_failure()
467 	count = rte_dma_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error);  in test_single_item_status_query_with_failure()
482 				fail_idx, status_count, COMP_BURST_SZ - count);  in test_single_item_status_query_with_failure()
491 	count2 = rte_dma_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error);  in test_single_item_status_query_with_failure()
495 	if (count + status_count + count2 != COMP_BURST_SZ)  in test_single_item_status_query_with_failure()
497 				count + status_count + count2, COMP_BURST_SZ);  in test_single_item_status_query_with_failure()
507 	enum rte_dma_status_code status[COMP_BURST_SZ];  in test_multi_failure()
513 	for (j = 0; j < COMP_BURST_SZ; j++) {  in test_multi_failure()
529 	count = rte_dma_completed_status(dev_id, vchan, COMP_BURST_SZ, NULL, status);  in test_multi_failure()
530 	while (count < COMP_BURST_SZ) {  in test_multi_failure()
533 		uint16_t ret = rte_dma_completed_status(dev_id, vchan, COMP_BURST_SZ - count,  in test_multi_failure()
537 					count, COMP_BURST_SZ);  in test_multi_failure()
549 	for (j = 0; j < COMP_BURST_SZ; j++) {  in test_multi_failure()
567 	while (count + err_count < COMP_BURST_SZ) {  in test_multi_failure()
568 		count += rte_dma_completed(dev_id, vchan, COMP_BURST_SZ, NULL, &error);  in test_multi_failure()
589 	struct rte_mbuf *srcs[COMP_BURST_SZ], *dsts[COMP_BURST_SZ];  in test_completion_status()
592 	for (i = 0; i < COMP_BURST_SZ; i++) {  in test_completion_status()
614 	for (i = 0; i < COMP_BURST_SZ; i++) {  in test_completion_status()