[TableGen] Use llvm::append_range (NFC)

[llvm] Use *Map::lookup (NFC)

[X86] Add x86_amx type for intel AMX.

The x86_amx is used for AMX intrisics. <256 x i32> is bitcast to x86_amx when
it is used by AMX intrinsics, and x86_amx is bitcast to <256 x i32> when it
is use

[X86] Add x86_amx type for intel AMX.

The x86_amx is used for AMX intrisics. <256 x i32> is bitcast to x86_amx when
it is used by AMX intrinsics, and x86_amx is bitcast to <256 x i32> when it
is used by load/store instruction. So amx intrinsics only operate on type x86_amx.
It can help to separate amx intrinsics from llvm IR instructions (+-*/).
Thank Craig for the idea. This patch depend on https://reviews.llvm.org/D87981.

Differential Revision: https://reviews.llvm.org/D91927

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[TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem.

These properties aren't additive. They are closer to ReadOnly and
WriteOnly. The default is ReadWrite. ReadMem cancels the write p

[TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem.

These properties aren't additive. They are closer to ReadOnly and
WriteOnly. The default is ReadWrite. ReadMem cancels the write property and
WriteMem cancels the read property. Combining them leaves neither.

This patch checks that when we process WriteMem, the Mod flag is
still set. And for ReadMem we check that the Ref flag set still set.

I've updated 2 target intrinsics that were combining these properties.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D93571

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[Tablegen] Use llvm::is_contained (NFC)

[TableGen] [CodeGenTarget] Cache the target's instruction namespace.

Differential Revision: https://reviews.llvm.org/D92722

[TableGen] Add frontend/backend phase timing capability.

Describe in the BackEnd Developer's Guide. Instrument a few backends.

Remove an old unused timing facility. Add a null backend for timing
th

[TableGen] Add frontend/backend phase timing capability.

Describe in the BackEnd Developer's Guide. Instrument a few backends.

Remove an old unused timing facility. Add a null backend for timing
the parser.

Differential Revision: https://reviews.llvm.org/D91388

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[WebAssembly] Implementation of (most) table instructions

Implementation of instructions table.get, table.set, table.grow,
table.size, table.fill, table.copy.

Missing instructions are table.init an

[WebAssembly] Implementation of (most) table instructions

Implementation of instructions table.get, table.set, table.grow,
table.size, table.fill, table.copy.

Missing instructions are table.init and elem.drop as they deal with
element sections which are not yet implemented.

Added more tests to tables.s

Differential Revision: https://reviews.llvm.org/D89797

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[IR][FIX] Intrinsics - don't apply default willreturn if IntrNoReturn is specified

Summary: Since willreturn will soon be added as default attribute, we can end up with both noreturn and willreturn

[IR][FIX] Intrinsics - don't apply default willreturn if IntrNoReturn is specified

Summary: Since willreturn will soon be added as default attribute, we can end up with both noreturn and willreturn on the same intrinsic. This was exposed by llvm.wasm.throw which has IntrNoReturn.

Reviewers: jdoerfert, arsenm

Differential Revision: https://reviews.llvm.org/D88644

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[VE] Add new MVT types for NEC SX Aurora VE vector

This patch adds entries for:
v64i64
v128i64
v256i64
v64f64
v128f64
v256f64

Reviewed By: simoll

Differential Revision: htt

[VE] Add new MVT types for NEC SX Aurora VE vector

This patch adds entries for:
v64i64
v128i64
v256i64
v64f64
v128f64
v256f64

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D88776

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[PowerPC] Add vector pair load/store instructions and vector pair register class

This patch adds support for the lxvp, lxvpx, plxvp, stxvp, stxvpx and pstxvp
instructions in the PowerPC backend. The

[PowerPC] Add vector pair load/store instructions and vector pair register class

This patch adds support for the lxvp, lxvpx, plxvp, stxvp, stxvpx and pstxvp
instructions in the PowerPC backend. These instructions allow loading and
storing VSX register pairs. This patch also adds the VSRp register class
definition needed for these instructions.

Differential Revision: https://reviews.llvm.org/D84359

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[TableGen][GlobalISel] Fix handling of zero_reg

When generating matching tables for GlobalISel, TableGen would output
"::zero_reg" whenever encountering the zero_reg, which in turn would
result in c

[TableGen][GlobalISel] Fix handling of zero_reg

When generating matching tables for GlobalISel, TableGen would output
"::zero_reg" whenever encountering the zero_reg, which in turn would
result in compilation error. This patch fixes that by instead outputting
NoRegister (== 0), which is the same result that TableGen produces when
generating matching tables for ISelDAG.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D86215

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[IR] Add NoUndef attribute to Intrinsics.td

This patch adds NoUndef to Intrinsics.td.
The attribute is attached to llvm.assume's operand, because llvm.assume(undef)
is UB.
It is attached to pointer

[IR] Add NoUndef attribute to Intrinsics.td

This patch adds NoUndef to Intrinsics.td.
The attribute is attached to llvm.assume's operand, because llvm.assume(undef)
is UB.
It is attached to pointer operands of several memory accessing intrinsics
as well.

This change makes ValueTracking::getGuaranteedNonPoisonOps' intrinsic check
unnecessary, so it is removed.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D86576

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Reland [IR] Intrinsics default attributes and opt-out flag

Intrinsic properties can now be set to default and applied to all
intrinsics. If the attributes are not needed, the user can opt-out by
set

Reland [IR] Intrinsics default attributes and opt-out flag

Intrinsic properties can now be set to default and applied to all
intrinsics. If the attributes are not needed, the user can opt-out by
setting the DisableDefaultAttributes flag to true.

Differential Revision: https://reviews.llvm.org/D70365

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Revert "[IR] Intrinsics default attributes and opt-out flag"

This commit introduced a non-trivial compile time regression that needs
to be addressed: https://reviews.llvm.org/D70365#2227627
Given th

Revert "[IR] Intrinsics default attributes and opt-out flag"

This commit introduced a non-trivial compile time regression that needs
to be addressed: https://reviews.llvm.org/D70365#2227627
Given that it is unclear how long that will take, I'll revert it for
now.

This reverts commit eedf18fc1f5fc71bb896204abf41fc5a2dbf25f7.

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[IR] Intrinsics default attributes and opt-out flag

Intrinsic properties can now be set to default and applied to all
intrinsics. If the attributes are not needed, the user can opt-out by
setting th

[IR] Intrinsics default attributes and opt-out flag

Intrinsic properties can now be set to default and applied to all
intrinsics. If the attributes are not needed, the user can opt-out by
setting the DisableDefaultAttributes flag to true.

Differential Revision: https://reviews.llvm.org/D70365

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[MVT] Add new MVT types for RISC-V vector.

In RISC-V vector extension, users could group multiple vector registers
as one pseudo register. In mixed width operations, users could use
partial vector r

[MVT] Add new MVT types for RISC-V vector.

In RISC-V vector extension, users could group multiple vector registers
as one pseudo register. In mixed width operations, users could use
partial vector registers to reduce the register pressure. The parameter
to control register grouping and partial use is called LMUL. LMUL is a
part of the type. So, we have a bunch of vector types. In order to
support all these types, we need new MVT types in LLVM. In this patch, I
added several MVT types that are used in RISC-V vector implementation.
This is a standalone patch for MVT types without RISC-V related implementation.

Differential revision: https://reviews.llvm.org/D81724

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[IR] NoFree IntrinsicProperty.

Summary:
Separate introduction of IntrNoFree property as suggested in D70365

Reviewers: arsenm, nhaehnle

Tags: #llvm

Differential Revision: https://reviews.llvm.org

[IR] NoFree IntrinsicProperty.

Summary:
Separate introduction of IntrNoFree property as suggested in D70365

Reviewers: arsenm, nhaehnle

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82587

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[MVT] Add missing floating point types for 1024/2048-bit vectors.

Summary:
This patch adds entries for:
v64f16
v128f16
v64bf16
v128bf16
v32f64

Subscribers: dschuff, hiraditya, aheejin, ll

[MVT] Add missing floating point types for 1024/2048-bit vectors.

Summary:
This patch adds entries for:
v64f16
v128f16
v64bf16
v128bf16
v32f64

Subscribers: dschuff, hiraditya, aheejin, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82466

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Enable `align <n>` to be used in the intrinsic definition.

- This allow us to specify the (minimal) alignment on an intrinsic's
arguments and, more importantly, the return value.

Differential Rev

Enable `align <n>` to be used in the intrinsic definition.

- This allow us to specify the (minimal) alignment on an intrinsic's
arguments and, more importantly, the return value.

Differential Revision: https://reviews.llvm.org/D80422

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Refactor argument attribute specification in intrinsic definition. NFC.

- Argument attribute needs specifiying through `ArgIndex<n>`
(corresponding to `FirstArgIndex`) to distinguish explicitly fr

Refactor argument attribute specification in intrinsic definition. NFC.

- Argument attribute needs specifiying through `ArgIndex<n>`
(corresponding to `FirstArgIndex`) to distinguish explicitly from the
index number from the overloaded type list.
- In addition, `RetIndex` (corresponding to `ReturnIndex`) and
`FuncIndex` (corresponding to `FunctionIndex`) are introduced for us
to associate attributes on the return value and potentially function
itself.

Differential Revision: https://reviews.llvm.org/D80422

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[CodeGen][BFloat] Add bfloat MVT type

Summary:
This patch adds BFloat MVT support. It also adds fixed and scalable vector MVT
types for BFloat.

This patch is part of a series that adds support for

[CodeGen][BFloat] Add bfloat MVT type

Summary:
This patch adds BFloat MVT support. It also adds fixed and scalable vector MVT
types for BFloat.

This patch is part of a series that adds support for the Bfloat16 extension of the Armv8.6-a architecture, as
detailed here:

https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a

The bfloat type, and its properties are specified in the Arm Architecture
Reference Manual:

https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile

Reviewers: aemerson, huntergr, craig.topper, fpetrogalli, sdesmalen, LukeGeeson, ostannard

Reviewed By: ostannard

Subscribers: LukeGeeson, pbarrio, dschuff, kristof.beyls, hiraditya, aheejin, jdoerfert, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D79706

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Add v16f64 value type

We need to use it to handle <16 x double> indirect indexes
in the AMDGPU BE.

The only visible change from adding it is in ARM cost model.
To me it looks reasonable. With doubl

Add v16f64 value type

We need to use it to handle <16 x double> indirect indexes
in the AMDGPU BE.

The only visible change from adding it is in ARM cost model.
To me it looks reasonable. With doubling a vector size it
quadruples the cost up to the size 8 and then it did only
double it. Now it also quadruples, which seems a logical
progression to me.

Actual AMDGPU code is to follow, this is a common part, plus
load/store legalization in the AMDGPU BE not to break what
works now.

Differential Revision: https://reviews.llvm.org/D79952

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[VP,Integer,#1] Vector-predicated integer intrinsics

Summary:
This patch adds IR intrinsics for vector-predicated integer arithmetic.

It is subpatch #1 of the [integer
slice](https://reviews.llvm.o

[VP,Integer,#1] Vector-predicated integer intrinsics

Summary:
This patch adds IR intrinsics for vector-predicated integer arithmetic.

It is subpatch #1 of the [integer
slice](https://reviews.llvm.org/D57504#1732277) of
[LLVM-VP](https://reviews.llvm.org/D57504). LLVM-VP is a larger effort to bring
native vector predication to LLVM.

Reviewed By: andrew.w.kaylor

Differential Revision: https://reviews.llvm.org/D69891

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Make llvm::StringRef to std::string conversions explicit.

This is how it should've been and brings it more in line with
std::string_view. There should be no functional change here.

This is mostly m

Make llvm::StringRef to std::string conversions explicit.

This is how it should've been and brings it more in line with
std::string_view. There should be no functional change here.

This is mostly mechanical from a custom clang-tidy check, with a lot of
manual fixups. It uncovers a lot of minor inefficiencies.

This doesn't actually modify StringRef yet, I'll do that in a follow-up.

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