factor copy and paste code.

llvm-svn: 98908

look up instructions by record, not by name.

llvm-svn: 98904

Completely rewrite tblgen's type inference mechanism,
changing the primary datastructure from being a
"std::vector<unsigned char>" to being a new TypeSet class
that actually has (gasp) invariants!

Completely rewrite tblgen's type inference mechanism,
changing the primary datastructure from being a
"std::vector<unsigned char>" to being a new TypeSet class
that actually has (gasp) invariants!

This changes more things than I remember, but one major
innovation here is that it enforces that named input
values agree in type with their output values.

This also eliminates code that transparently assumes (in
some cases) that SDNodeXForm input/output types are the
same, because this is wrong in many case.

This also eliminates a bug which caused a lot of ambiguous
patterns to go undetected, where a register class would
sometimes pick the first possible type, causing an
ambiguous pattern to get arbitrary results.

With all the recent target changes, this causes no
functionality change!

llvm-svn: 98534

show more ...

move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start u

move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.

llvm-svn: 95687

show more ...

Remove DEBUG_DECLARE, looks like we don't need it.
Also, DEBUG_VALUE has side effects.

llvm-svn: 93498

Add DEBUG_DECLARE. Not used yet.

llvm-svn: 93040

Add DEBUG_VALUE. Not used yet.

llvm-svn: 93030

Remove the CPAttrParentAsRoot code, which is unused, and inconvenient
for a refactoring I'm working on.

llvm-svn: 92503

Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
unused DECLARE instruction.

KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places wher

Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
unused DECLARE instruction.

KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.

llvm-svn: 83006

show more ...

Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713

Fix a few more places in TableGen that need to handle EVT::vAny types.

llvm-svn: 78643

Add a new overloaded EVT::vAny type for use in TableGen to allow intrinsic
arguments that are vectors of any size and element type.

llvm-svn: 78631

Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.

llvm-svn: 78610

Match X86 register names to number.

llvm-svn: 77404

Remove the v3i32 and v3f32 value types: they are not
native for any supported targets.

llvm-svn: 75785

Revert 75308.

llvm-svn: 75565

Add new vector types for 192-bit, 348-bit and 512-bit sizes.
These are needed to represent ARM Neon struct datatypes containing 2, 3 or 4
separate vectors.

llvm-svn: 75308

Refactor TableGen's llvm::getName to share code with llvm::getEnumName,
since names are the same for almost all the types.

llvm-svn: 75302

Add new ValueType for metadata.

llvm-svn: 74882

Replace std::iostreams with raw_ostream in TableGen.
- Sorry, I can't help myself.

- No intended functionality change.

llvm-svn: 74742

Add more vector ValueTypes for AVX and other extended vector instruction
sets.

llvm-svn: 74427

Revert 72707 and 72709, for the moment.

llvm-svn: 72712

Make the implicit inputs and outputs of target-independent
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust
all target-inde

Make the implicit inputs and outputs of target-independent
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.

Most targets will still produce a Flag-setting target-dependent
version when selection is done. X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted. All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly. The
same can be done on other targets.

The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.

llvm-svn: 72707

show more ...

Fix PR3994: LLVMMatchType arguments do not refer to absolute return value
and argument positions but only to the overloaded intrinsic parameters.
Keep a separate list of these overloaded parameters i

Fix PR3994: LLVMMatchType arguments do not refer to absolute return value
and argument positions but only to the overloaded intrinsic parameters.
Keep a separate list of these overloaded parameters in CodeGenTarget.cpp
so they can be resolved easily. Remove assertions from IntrinsicEmitter.cpp:
they were harmless but confusing, and the assertions elsewhere in TableGen
will catch any incorrect values.

llvm-svn: 69316

show more ...

Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize
it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.

llvm-svn: 68986