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Revision tags: llvmorg-7.0.1, llvmorg-7.0.1-rc3 |
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ca29c271 |
| 07-Dec-2018 |
David Green <[email protected]> |
[Targets] Add errors for tiny and kernel codemodel on targets that don't support them
Adds fatal errors for any target that does not support the Tiny or Kernel codemodels by rejigging the getEffecti
[Targets] Add errors for tiny and kernel codemodel on targets that don't support them
Adds fatal errors for any target that does not support the Tiny or Kernel codemodels by rejigging the getEffectiveCodeModel calls.
Differential Revision: https://reviews.llvm.org/D50141
llvm-svn: 348585
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Revision tags: llvmorg-7.0.1-rc2, llvmorg-7.0.1-rc1, llvmorg-7.0.0, llvmorg-7.0.0-rc3, llvmorg-7.0.0-rc2, llvmorg-7.0.0-rc1, llvmorg-6.0.1, llvmorg-6.0.1-rc3, llvmorg-6.0.1-rc2, llvmorg-6.0.1-rc1, llvmorg-5.0.2, llvmorg-5.0.2-rc2 |
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6054e650 |
| 23-Mar-2018 |
David Blaikie <[email protected]> |
Move TargetLoweringObjectFile from CodeGen to Target to fix layering
It's implemented in Target & include from other Target headers, so the header should be in Target.
llvm-svn: 328392
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Revision tags: llvmorg-5.0.2-rc1, llvmorg-6.0.0, llvmorg-6.0.0-rc3, llvmorg-6.0.0-rc2, llvmorg-6.0.0-rc1 |
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26d11ca4 |
| 22-Dec-2017 |
Sanjoy Das <[email protected]> |
(Re-landing) Expose a TargetMachine::getTargetTransformInfo function
Re-land r321234. It had to be reverted because it broke the shared library build. The shared library build broke because there
(Re-landing) Expose a TargetMachine::getTargetTransformInfo function
Re-land r321234. It had to be reverted because it broke the shared library build. The shared library build broke because there was a missing LLVMBuild dependency from lib/Passes (which calls TargetMachine::getTargetIRAnalysis) to lib/Target. As far as I can tell, this problem was always there but was somehow masked before (perhaps because TargetMachine::getTargetIRAnalysis was a virtual function).
Original commit message:
This makes the TargetMachine interface a bit simpler. We still need the std::function in TargetIRAnalysis to avoid having to add a dependency from Analysis to Target.
See discussion: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119749.html
I avoided adding all of the backend owners to this review since the change is simple, but let me know if you feel differently about this.
Reviewers: echristo, MatzeB, hfinkel
Reviewed By: hfinkel
Subscribers: jholewinski, jfb, arsenm, dschuff, mcrosier, sdardis, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, llvm-commits
Differential Revision: https://reviews.llvm.org/D41464
llvm-svn: 321375
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747d1114 |
| 21-Dec-2017 |
Sanjoy Das <[email protected]> |
Revert "Expose a TargetMachine::getTargetTransformInfo function"
This reverts commit r321234. It breaks the -DBUILD_SHARED_LIBS=ON build.
llvm-svn: 321243
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0c3de350 |
| 21-Dec-2017 |
Sanjoy Das <[email protected]> |
Expose a TargetMachine::getTargetTransformInfo function
Summary: This makes the TargetMachine interface a bit simpler. We still need the std::function in TargetIRAnalysis to avoid having to add a d
Expose a TargetMachine::getTargetTransformInfo function
Summary: This makes the TargetMachine interface a bit simpler. We still need the std::function in TargetIRAnalysis to avoid having to add a dependency from Analysis to Target.
See discussion: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119749.html
I avoided adding all of the backend owners to this review since the change is simple, but let me know if you feel differently about this.
Reviewers: echristo, MatzeB, hfinkel
Reviewed By: hfinkel
Subscribers: jholewinski, jfb, arsenm, dschuff, mcrosier, sdardis, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, llvm-commits
Differential Revision: https://reviews.llvm.org/D41464
llvm-svn: 321234
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Revision tags: llvmorg-5.0.1, llvmorg-5.0.1-rc3, llvmorg-5.0.1-rc2 |
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b3bde2ea |
| 17-Nov-2017 |
David Blaikie <[email protected]> |
Fix a bunch more layering of CodeGen headers that are in Target
All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, n
Fix a bunch more layering of CodeGen headers that are in Target
All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around).
llvm-svn: 318490
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Revision tags: llvmorg-5.0.1-rc1 |
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bb8507e6 |
| 12-Oct-2017 |
Matthias Braun <[email protected]> |
Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine"
Reverting to investigate layering effects of MCJIT not linking libCodeGen but using TargetMachine::getNameWithPrefix() breaking the
Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine"
Reverting to investigate layering effects of MCJIT not linking libCodeGen but using TargetMachine::getNameWithPrefix() breaking the lldb bots.
This reverts commit r315633.
llvm-svn: 315637
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3a9c114b |
| 12-Oct-2017 |
Matthias Braun <[email protected]> |
TargetMachine: Merge TargetMachine and LLVMTargetMachine
Merge LLVMTargetMachine into TargetMachine.
- There is no in-tree target anymore that just implements TargetMachine but not LLVMTargetMach
TargetMachine: Merge TargetMachine and LLVMTargetMachine
Merge LLVMTargetMachine into TargetMachine.
- There is no in-tree target anymore that just implements TargetMachine but not LLVMTargetMachine. - It should still be possible to stub out all the various functions in case a target does not want to use lib/CodeGen - This simplifies the code and avoids methods ending up in the wrong interface.
Differential Revision: https://reviews.llvm.org/D38489
llvm-svn: 315633
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Revision tags: llvmorg-5.0.0, llvmorg-5.0.0-rc5, llvmorg-5.0.0-rc4, llvmorg-5.0.0-rc3, llvmorg-5.0.0-rc2 |
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79e238af |
| 03-Aug-2017 |
Rafael Espindola <[email protected]> |
Delete Default and JITDefault code models
IMHO it is an antipattern to have a enum value that is Default.
At any given piece of code it is not clear if we have to handle Default or if has already b
Delete Default and JITDefault code models
IMHO it is an antipattern to have a enum value that is Default.
At any given piece of code it is not clear if we have to handle Default or if has already been mapped to a concrete value. In this case in particular, only the target can do the mapping and it is nice to make sure it is always done.
This deletes the two default enum values of CodeModel and uses an explicit Optional<CodeModel> when it is possible that it is unspecified.
llvm-svn: 309911
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Revision tags: llvmorg-5.0.0-rc1 |
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89ca10de |
| 14-Jul-2017 |
Jonas Paulsson <[email protected]> |
[SystemZ] Enable LoopDataPrefetch pass.
Loop data prefetching has shown some improvements on benchmarks, and is enabled at -O1 and above.
Review: Ulrich Weigand llvm-svn: 308024
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Revision tags: llvmorg-4.0.1, llvmorg-4.0.1-rc3 |
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6bda14b3 |
| 06-Jun-2017 |
Chandler Carruth <[email protected]> |
Sort the remaining #include lines in include/... and lib/....
I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line
Sort the remaining #include lines in include/... and lib/....
I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days.
I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch.
This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files.
Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again).
llvm-svn: 304787
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Revision tags: llvmorg-4.0.1-rc2 |
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5e394c3d |
| 30-May-2017 |
Matthias Braun <[email protected]> |
TargetPassConfig: Keep a reference to an LLVMTargetMachine; NFC
TargetPassConfig is not useful for targets that do not use the CodeGen library, so we may just as well store a pointer to an LLVMTarge
TargetPassConfig: Keep a reference to an LLVMTargetMachine; NFC
TargetPassConfig is not useful for targets that do not use the CodeGen library, so we may just as well store a pointer to an LLVMTargetMachine instead of just to a TargetMachine.
While at it, also change the constructor to take a reference instead of a pointer as the TM must not be nullptr.
llvm-svn: 304247
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Revision tags: llvmorg-4.0.1-rc1, llvmorg-4.0.0, llvmorg-4.0.0-rc4, llvmorg-4.0.0-rc3, llvmorg-4.0.0-rc2 |
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3943d2b0 |
| 24-Jan-2017 |
Eugene Zelenko <[email protected]> |
[SystemZ] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 292983
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Revision tags: llvmorg-4.0.0-rc1, llvmorg-3.9.1, llvmorg-3.9.1-rc3, llvmorg-3.9.1-rc2, llvmorg-3.9.1-rc1 |
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524f276c |
| 28-Nov-2016 |
Ulrich Weigand <[email protected]> |
[SystemZ] Improve use of conditional instructions
This patch moves formation of LOC-type instructions from (late) IfConversion to the early if-conversion pass, and in some cases additionally creates
[SystemZ] Improve use of conditional instructions
This patch moves formation of LOC-type instructions from (late) IfConversion to the early if-conversion pass, and in some cases additionally creates them directly from select instructions during DAG instruction selection.
To make early if-conversion work, the patch implements the canInsertSelect / insertSelect callbacks. It also implements the commuteInstructionImpl and FoldImmediate callbacks to enable generation of the full range of LOC instructions.
Finally, the patch adds support for all instructions of the load-store-on-condition-2 facility, which allows using LOC instructions also for high registers.
Due to the use of the GRX32 register class to enable high registers, we now also have to handle the cases where there are still no single hardware instructions (conditional move from a low register to a high register or vice versa). These are converted back to a branch sequence after register allocation. Since the expandRAPseudos callback is not allowed to create new basic blocks, this requires a simple new pass, modelled after the ARM/AArch64 ExpandPseudos pass.
Overall, this patch causes significantly more LOC-type instructions to be used, and results in a measurable performance improvement.
llvm-svn: 288028
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28f29487 |
| 09-Nov-2016 |
Jonas Paulsson <[email protected]> |
[MachineScheduler] Comments fixing.
The name/comment of the third argument to the ScheduleDAGMI constructor is RemoveKillFlags and not IsPostRA. Only the comments are changed.
Review: A Trick llvm-
[MachineScheduler] Comments fixing.
The name/comment of the third argument to the ScheduleDAGMI constructor is RemoveKillFlags and not IsPostRA. Only the comments are changed.
Review: A Trick llvm-svn: 286350
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8010b631 |
| 20-Oct-2016 |
Jonas Paulsson <[email protected]> |
[SystemZ] Post-RA scheduler implementation
Post-RA sched strategy and scheduling instruction annotations for z196, zEC12 and z13.
This scheduler optimizes decoder grouping and balances processor re
[SystemZ] Post-RA scheduler implementation
Post-RA sched strategy and scheduling instruction annotations for z196, zEC12 and z13.
This scheduler optimizes decoder grouping and balances processor resources (including side steering the FPd unit instructions).
The SystemZHazardRecognizer keeps track of the scheduling state, which can be dumped with -debug-only=misched.
Reviers: Ulrich Weigand, Andrew Trick. https://reviews.llvm.org/D17260
llvm-svn: 284704
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f42454b9 |
| 09-Oct-2016 |
Mehdi Amini <[email protected]> |
Move the global variables representing each Target behind accessor function
This avoids "static initialization order fiasco"
Differential Revision: https://reviews.llvm.org/D25412
llvm-svn: 283702
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Revision tags: llvmorg-3.9.0, llvmorg-3.9.0-rc3, llvmorg-3.9.0-rc2, llvmorg-3.9.0-rc1 |
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cf7cc724 |
| 10-Jul-2016 |
Marcin Koscielnicki <[email protected]> |
[SystemZ] Utilize Test Data Class instructions.
This adds a new SystemZ-specific intrinsic, llvm.s390.tdc.f(32|64|128), which maps straight to the test data class instructions. A new IR pass is add
[SystemZ] Utilize Test Data Class instructions.
This adds a new SystemZ-specific intrinsic, llvm.s390.tdc.f(32|64|128), which maps straight to the test data class instructions. A new IR pass is added to recognize instructions that can be converted to TDC and perform the necessary replacements.
Differential Revision: http://reviews.llvm.org/D21949
llvm-svn: 275016
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Revision tags: llvmorg-3.8.1, llvmorg-3.8.1-rc1 |
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8c34dd82 |
| 18-May-2016 |
Rafael Espindola <[email protected]> |
Delete Reloc::Default.
Having an enum member named Default is quite confusing: Is it distinct from the others?
This patch removes that member and instead uses Optional<Reloc> in places where we hav
Delete Reloc::Default.
Having an enum member named Default is quite confusing: Is it distinct from the others?
This patch removes that member and instead uses Optional<Reloc> in places where we have a user input that still hasn't been maped to the default value, which is now clear has no be one of the remaining 3 options.
llvm-svn: 269988
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31d19d43 |
| 10-May-2016 |
Matthias Braun <[email protected]> |
CodeGen: Move TargetPassConfig from Passes.h to an own header; NFC
Many files include Passes.h but only a fraction needs to know about the TargetPassConfig class. Move it into an own header. Also re
CodeGen: Move TargetPassConfig from Passes.h to an own header; NFC
Many files include Passes.h but only a fraction needs to know about the TargetPassConfig class. Move it into an own header. Also rename Passes.cpp to TargetPassConfig.cpp while we are at it.
llvm-svn: 269011
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2eb027d2 |
| 07-Apr-2016 |
Ulrich Weigand <[email protected]> |
[SystemZ] Implement conditional returns
Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion p
[SystemZ] Implement conditional returns
Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass.
Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them.
This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14.
Author: koriakin
Differential Revision: http://reviews.llvm.org/D17339
llvm-svn: 265689
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Revision tags: llvmorg-3.8.0, llvmorg-3.8.0-rc3, llvmorg-3.8.0-rc2, llvmorg-3.8.0-rc1 |
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e451eeff |
| 10-Dec-2015 |
Jonas Paulsson <[email protected]> |
[PostRA scheduling] Allow a target to do scheduling when it wants post RA.
SystemZ needs to do its scheduling after branch relaxation, which can only happen after block placement, and therefore the
[PostRA scheduling] Allow a target to do scheduling when it wants post RA.
SystemZ needs to do its scheduling after branch relaxation, which can only happen after block placement, and therefore the standard PostRAScheduler point in the pass sequence is too early.
TargetMachine::targetSchedulesPostRAScheduling() is a new method that signals on returning true that target will insert the final scheduling pass on its own.
Reviewed by Hal Finkel
llvm-svn: 255234
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Revision tags: llvmorg-3.7.1, llvmorg-3.7.1-rc2, llvmorg-3.7.1-rc1 |
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5d3fbd37 |
| 08-Oct-2015 |
Jonas Paulsson <[email protected]> |
[SystemZ] SystemZElimCompare pass improved.
Compare elimination extended to recognize load-and-test instructions used for comparison and eliminate them the same way as with compare instructions.
Te
[SystemZ] SystemZElimCompare pass improved.
Compare elimination extended to recognize load-and-test instructions used for comparison and eliminate them the same way as with compare instructions.
Test case fp-cmp-05.ll updated to expect optimized results now also for z13.
The order of instruction shortening and compare elimination passes have been changed so that opcodes do not have to be handled in both passes.
Reviewed by Ulrich Weigand.
llvm-svn: 249666
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a4e5d3cf |
| 16-Sep-2015 |
Eric Christopher <[email protected]> |
constify the Function parameter to the TTI creation callback and propagate to all callers/users/etc.
llvm-svn: 247864
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e4405e94 |
| 10-Sep-2015 |
Chandler Carruth <[email protected]> |
[ADT] Switch a bunch of places in LLVM that were doing single-character splits to actually use the single character split routine which does less work, and in a debug build is *substantially* faster.
[ADT] Switch a bunch of places in LLVM that were doing single-character splits to actually use the single character split routine which does less work, and in a debug build is *substantially* faster.
llvm-svn: 247245
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