Switch a number of loops in lib/CodeGen over to range-based for-loops, now that
the MachineRegisterInfo iterators are compatible with it.

llvm-svn: 204075

Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing
operator* on the by-operand iterators to return a MachineOperand& rather than
a MachineInstr&. At this point they almost

Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing
operator* on the by-operand iterators to return a MachineOperand& rather than
a MachineInstr&. At this point they almost behave like normal iterators!

Again, this requires making some existing loops more verbose, but should pave
the way for the big range-based for-loop cleanups in the future.

llvm-svn: 203865

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[C++11] Add 'override' keyword to virtual methods that override their base class.

llvm-svn: 203220

Fix typo

llvm-svn: 191964

Tidy up a few more uses of MF.getFunction()->getName().

Based on CR feedback from r162301 and Craig Topper's refactoring in r162347
here are a few other places that could use the same API (& in one

Tidy up a few more uses of MF.getFunction()->getName().

Based on CR feedback from r162301 and Craig Topper's refactoring in r162347
here are a few other places that could use the same API (& in one instance drop
a Function.h dependency).

llvm-svn: 162367

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Run ProcessImplicitDefs on SSA form where it can be much simpler.

Implicitly defined virtual registers can simply have the <undef> bit set
on all uses, and copies can be turned into implicit defs re

Run ProcessImplicitDefs on SSA form where it can be much simpler.

Implicitly defined virtual registers can simply have the <undef> bit set
on all uses, and copies can be turned into implicit defs recursively.

Physical registers are a bit trickier. We handle the common case where a
physreg def is used by a nearby instruction in the same basic block. For
more complicated cases, just leave the IMPLICIT_DEF instruction in.

llvm-svn: 159149

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Remove ProcessImplicitDefs.h which was unused.

The ProcessImplicitDefs class can be local to its implementation file.

llvm-svn: 159041

Switch all register list clients to the new MC*Iterator interface.

No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in

Switch all register list clients to the new MC*Iterator interface.

No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

llvm-svn: 157854

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Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.

llvm-svn: 152016

RegAlloc superpass: includes phi elimination, coalescing, and scheduling.

Creates a configurable regalloc pipeline.

Ensure specific llc options do what they say and nothing more: -reglloc=... has n

RegAlloc superpass: includes phi elimination, coalescing, and scheduling.

Creates a configurable regalloc pipeline.

Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa.

When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>.

CodeGen transformation passes are never "required" as an analysis

ProcessImplicitDefs does not require LiveVariables.

We have a plan to massively simplify some of the early passes within the regalloc superpass.

llvm-svn: 150226

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Improve sub-register def handling in ProcessImplicitDefs.

This boils down to using MachineOperand::readsReg() more.

This fixes PR11829 where a use ended up after the first def when
lowering REG_SEQ

Improve sub-register def handling in ProcessImplicitDefs.

This boils down to using MachineOperand::readsReg() more.

This fixes PR11829 where a use ended up after the first def when
lowering REG_SEQUENCE instructions involving IMPLICIT_DEFs.

llvm-svn: 148996

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Handle REG_SEQUENCE with implicitly defined operands.

Code like that would only be produced by bugpoint, but we should still
handle it correctly.

When a register is defined by a REG_SEQUENCE of und

Handle REG_SEQUENCE with implicitly defined operands.

Code like that would only be produced by bugpoint, but we should still
handle it correctly.

When a register is defined by a REG_SEQUENCE of undefs, the register
itself is undef. Previously, we would create a register with uses but no
defs.

Fixes part of PR10520.

llvm-svn: 136401

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Place context in member variables instead of passing around pointers.

Use the opportunity to get rid of the trailing underscore variable names.

llvm-svn: 127618

None of the other pass names in CodeGen have terminating periods.

llvm-svn: 122628

Begin adding static dependence information to passes, which will allow us to
perform initialization without static constructors AND without explicit initialization
by the client. For the moment, pas

Begin adding static dependence information to passes, which will allow us to
perform initialization without static constructors AND without explicit initialization
by the client. For the moment, passes are required to initialize both their
(potential) dependencies and any passes they preserve. I hope to be able to relax
the latter requirement in the future.

llvm-svn: 116334

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Now with fewer extraneous semicolons!

llvm-svn: 115996

Fix batch of converting RegisterPass<> to INTIALIZE_PASS().

llvm-svn: 109045

Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.

TII::isMoveInstr is going tobe completely removed.

llvm-svn: 108507

Teach ProcessImplicitDefs to transform more COPY instructions into IMPLICIT_DEF (and subsequently eliminate them). This allows machine LICM to hoist IMPLICIT_DEF's. PR7620.

llvm-svn: 108304

Convert EXTRACT_SUBREG to COPY when emitting machine instrs.

EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and

Convert EXTRACT_SUBREG to COPY when emitting machine instrs.

EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.

llvm-svn: 107879

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Remove references to INSERT_SUBREG after de-SSA.

Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of
INSERT_SUBREG.

llvm-svn: 107878

Revert "Remove references to INSERT_SUBREG after de-SSA" r107725.

Buildbot breakage.

llvm-svn: 107744

Remove references to INSERT_SUBREG after de-SSA

llvm-svn: 107732

Convert INSERT_SUBREG to COPY in TwoAddressInstructionPass.

INSERT_SUBREG will now only appear in SSA machine instructions.

Fix the handling of partial redefs in ProcessImplicitDefs. This is now re

Convert INSERT_SUBREG to COPY in TwoAddressInstructionPass.

INSERT_SUBREG will now only appear in SSA machine instructions.

Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant
since partial redef COPY instructions appear.

llvm-svn: 107726

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Detect and handle COPY in many places.

This code is transitional, it will soon be possible to eliminate
isExtractSubreg, isInsertSubreg, and isMoveInstr in most places.

llvm-svn: 107547